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Reducing digital test volume using test point insertion
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Reducing digital test volume using test point insertion
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Sethuram
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Rajamani
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Rajamani Sethuram
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Bushnell
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Michael
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Michael L. Bushnell
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dissertation committee chair
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Peter
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Peter Meer
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Parashar
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Manish
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Advisory Committee
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Manish Parashar
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Chakraborty
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Tapan
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Tapan J Chakraborty
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Chakradhar
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Srimat
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Srimat Chakradhar
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Rutgers University
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Graduate School - New Brunswick
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theses
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2008
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2008-01
Language
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English
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electronic
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xii, 109 pages
Abstract
Test cost accounts for more than 40% of the entire cost for making a chip. This figure is expected to grow even higher in the future. Two major factors that determine test cost are a) test volume and b) test application time. Several
techniques such as compaction and compression have been proposed in the past to keep the test cost under an acceptable limit. However, due to the ever increasing size of today's digital very large scale integrated circuits, all prior known test cost reduction techniques are unable to keep the test cost under control.
In this dissertation, we present a new test point insertion (TPI) technique for regular cell-based application specific integrated chips (ASICs) and structured ASIC designs. The proposed technique can drastically reduce the test volume, the test application time and the test generation time. The TPI scheme facilitates the compression and the compaction algorithm to reduce test volume and test application time. By facilitating the automatic test pattern generation (ATPG) algorithm, we also reduce the test generation time. Test points are inserted using timing information, so they do not degrade performance. We present novel gain functions that quantify the reduction in test volume and ATPG time due to TPI and are used as heuristics to guide the selection of signal lines for inserting test points. We, then, show how test point insertion can be used to enhance the performance of a broadcast scan-based compressor. To further improve its performance, we use a new scan chain re-ordering algorithm to break the correlation that exists among different signal lines in the circuit due to a particular scan chain order.
Experiments conducted with ISCAS '89, ITC '99, and few industrial benchmarks clearly demonstrate the effectiveness and scalability of the proposed technique.
By using very little extra hardware for implementing test points and very little extra run time for the TPI step, we show that the test volume and test application can be reduced by up to 64.5% and test generation time can be reduced by up to 63.1% for structured ASIC designs. For the cell-based ASICs with broadcast scan compressors, experiments indicate that the proposed technique improves the compression by up to 46.6% and also reduces the overall ATPG CPU time by up to 49.3%.
techniques such as compaction and compression have been proposed in the past to keep the test cost under an acceptable limit. However, due to the ever increasing size of today's digital very large scale integrated circuits, all prior known test cost reduction techniques are unable to keep the test cost under control.
In this dissertation, we present a new test point insertion (TPI) technique for regular cell-based application specific integrated chips (ASICs) and structured ASIC designs. The proposed technique can drastically reduce the test volume, the test application time and the test generation time. The TPI scheme facilitates the compression and the compaction algorithm to reduce test volume and test application time. By facilitating the automatic test pattern generation (ATPG) algorithm, we also reduce the test generation time. Test points are inserted using timing information, so they do not degrade performance. We present novel gain functions that quantify the reduction in test volume and ATPG time due to TPI and are used as heuristics to guide the selection of signal lines for inserting test points. We, then, show how test point insertion can be used to enhance the performance of a broadcast scan-based compressor. To further improve its performance, we use a new scan chain re-ordering algorithm to break the correlation that exists among different signal lines in the circuit due to a particular scan chain order.
Experiments conducted with ISCAS '89, ITC '99, and few industrial benchmarks clearly demonstrate the effectiveness and scalability of the proposed technique.
By using very little extra hardware for implementing test points and very little extra run time for the TPI step, we show that the test volume and test application can be reduced by up to 64.5% and test generation time can be reduced by up to 63.1% for structured ASIC designs. For the cell-based ASICs with broadcast scan compressors, experiments indicate that the proposed technique improves the compression by up to 46.6% and also reduces the overall ATPG CPU time by up to 49.3%.
Note
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Ph.D.
Note
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Includes bibliographical references (p. 101-106).
Subject
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Topic
Electrical and Computer Engineering
Subject
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Topic
Application-specific integrated circuits
Subject
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Topic
Integrated circuits
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Graduate School - New Brunswick Electronic Theses and Dissertations
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rucore19991600001
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http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17215
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doi:10.7282/T35X299G
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ETD doctoral
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Rajamani Sethuram
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Rutgers University. Graduate School - New Brunswick
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I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
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