DescriptionRapid advances in the semiconductor industry have led to the proliferation of electric devices and information technology (IT). Integrated circuits(IC) based upon silicon MOSFET's have been used in virtually every electronic device produced today. The competitiveness of this huge market urges an increased device performance with lower cost. Over the past three decades, it is fulfilled by reducing transistor gate lengths and oxide thickness with each new generation of manufacturing technology. The leading edge CMOS technology is currently at the 45nm node with physical gate length at 18 nm and an equivalent gate oxide thickness (EOT) of 0.9 nm. However, as the device is miniaturized into the nanometer-scale regime nowadays, some challenges abound. Some challenges are new, some are just getting tougher and most of them will continue to become even more difficult to deal with for future generations. It is the world-wide effort to meet these challenges for sustaining the rapid growth of the industry. In this thesis, we will address a few of these challenges and offer some new approaches to get around them. Specifically, we introduce a new measurement technique to solve the precision problem in C-V measurement based on Time domain Reflectrometry(TDR). We also use the combination of experiment and theory to resolve the defect depth-profiling ambiguity associated with charge pumping measurement. Moreover, we find a new mode in transistor degradation that will become much more serious as the transistor size shrinks further. All these results represent a major and important advance which is also timely to the IC industry.