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Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors

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TitleInfo (displayLabel = Citation Title); (type = uniform)
Title
Diagnosis and error correction for a fault-tolerant arithmetic and logic unit for medical microprocessors
Name (ID = NAME001); (type = personal)
NamePart (type = family)
Savulimedu Veeravalli
NamePart (type = given)
Varadan
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Varadan Savulimedu Veeravalli
Role
RoleTerm (authority = RULIB)
author
Name (ID = NAME002); (type = personal)
NamePart (type = family)
Bushnell
NamePart (type = given)
Michael
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Advisory Committee
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Michael L. Bushnell
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chair
Name (ID = NAME003); (type = personal)
NamePart (type = family)
Marsic
NamePart (type = given)
Ivan
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Advisory Committee
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Ivan Marsic
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RoleTerm (authority = RULIB)
internal member
Name (ID = NAME004); (type = personal)
NamePart (type = family)
Parashar
NamePart (type = given)
Manish
Affiliation
Advisory Committee
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Manish Parashar
Role
RoleTerm (authority = RULIB)
internal member
Name (ID = NAME005); (type = corporate)
NamePart
Rutgers University
Role
RoleTerm (authority = RULIB)
degree grantor
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Graduate School - New Brunswick
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school
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Text
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theses
OriginInfo
DateCreated (qualifier = exact)
2008
DateOther (qualifier = exact); (type = degree)
2008-10
Language
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English
PhysicalDescription
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electronic
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application/pdf
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text/xml
Extent
xiv, 120 pages
Abstract
We present a fault tolerant Arithmetic and Logic Unit (ALU) for medical systems. Real-time medical systems possess stringent requirements for fault tolerance because faulty hardware could jeopardize human life. For such systems, checkers are employed so that incorrect data never leaves the faulty module and recovery time from faults is minimal. We have investigated information, hardware and time redundancy. After analyzing the hardware, the delay and the power overheads we have decided to use time redundancy as our fault tolerance method for the ALU.
The original contribution of this thesis is to provide single stuck-fault error correction in an ALU using recomputing with swapped operands (RESWO). Here, we divide the 32-bit data path into 3 equally-sized segments of 11 bits each, and then we swap the bit positions for the data in chunks of 11 bits. This requires multiplexing hardware to ensure that carries propagate correctly. We operate the ALU twice for each data path operation -- once normally, and once swapped. If there is a discrepancy, then either a bit position is broken or a carry propagation circuit is broken, and we diagnose the ALU using diagnosis vectors. First, we test the bit slices without generating carriers -- this requires three or four patterns to exercise each bit slice for stuck at 0 and stuck-at 1 faults. We test the carry chain for stuck-at faults and diagnose their location -- this requires two patterns, one to propagate a rising transition down the carry chain, and another to propagate a falling transition. Knowledge of the faulty bit slice and the fault in the carry path makes error correction possible by reconfiguring MUXes. It may be necessary to swap a third time and recompute to get more data to achieve full error correction.
The hardware overhead with the RESWO approach and the reconfiguration mechanism of one spare chunk for every sixteen chunks for the 64-bit ALU is 78%. The delay overhead for the 64-bit ALU with our fault-tolerance mechanism is 110.96%.
Note (type = degree)
M.S.
Note (type = bibliography)
Includes bibliographical references (p. 91-96).
Subject (ID = SUBJ1); (authority = RUETD)
Topic
Electrical and Computer Engineering
Subject (ID = SUBJ2); (authority = ETD-LCSH)
Topic
Computer arithmetic and logic units
Subject (ID = SUBJ3); (authority = ETD-LCSH)
Topic
Fault-tolerant computing
Subject (ID = SUBJ4); (authority = ETD-LCSH)
Topic
Microprocessors
Subject (ID = SUBJ5); (authority = ETD-LCSH)
Topic
Medicine--Data processing
RelatedItem (type = host)
TitleInfo
Title
Graduate School - New Brunswick Electronic Theses and Dissertations
Identifier (type = local)
rucore19991600001
Identifier (type = hdl)
http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17565
Identifier
ETD_1309
Location
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NjNbRU
Identifier (type = doi)
doi:10.7282/T3TQ61T7
Genre (authority = ExL-Esploro)
ETD graduate
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The author owns the copyright to this work.
Copyright
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Availability
Status
Open
AssociatedEntity (AUTHORITY = rulib); (ID = 1)
Name
Varadan Savulimedu Veeravalli
Role
Copyright holder
Affiliation
Rutgers University. Graduate School - New Brunswick
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Non-exclusive ETD license
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Author Agreement License
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I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
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