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Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability
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Ausoori, Raghuveer. Information theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability. Retrieved from https://doi.org/doi:10.7282/T3H70FXN

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TitleInformation theoretic and spectral methods of test point, partial-scan and full-scan flip-flop insertion to improve integrated circuit testability
NameAusoori, Raghuveer (author); Bushnell, Michael (chair); Chakraborty, Tapan (internal member); Agrawal, Vishwani (outside member); Chen, Xinghao (outside member); Rutgers University; Graduate School - New Brunswick
Date Created
Other Date2009-10 (degree)
SubjectElectrical and Computer Engineering, Integrated circuits, Integrated circuits--Testing
Extentxiii, 133 p. : ill.
DescriptionWe present a radically new design for testability (DFT) algorithm, which inserts test points (TPs) and scanned flip-flops (SFFs) into large circuits to make them testable. The algorithm measures testability using Shannon's entropy measure (from information theory), which will be shown to be a vastly superior way to measure testability, and spectral co-efficients. The spectral measures are superior in measuring fault coverage (FC) improvement. The algorithm can determine the DFT candidates using a gradient descent method or using an integer linear program (ILP). The optimal insertion of the TPs and SFFs reduces the amount of DFT hardware, since the algorithm trades off inserting a TP versus inserting a SFF. Various other derived measures are used and found to be effective in making the circuit testability better at various stages. The integer linear program finds the optimal solution to the optimization, and the testability measures are used to maximize information flow through the circuit-under-test (CUT). The result, on full-scan designs with test points, is a 40.05% reduction in test volume (TV) and a 54.24% reduction in test application time (TAT), compared to a full-scan design without test points. The method, used in conjunction with the Synopsys TetraMAX™ automatic test pattern generator (ATPG), achieves 1.55% higher FC and 100% fault efficiency (FE) on ITC ’99 benchmark circuits compared to conventional methods and reduces the ATPG time by 90.24%. The method works better than all prior methods on partial-scan circuits, as well. We achieve TV reductions of 19.56% and 33.42% and TAT reductions of 21.63% and 31.23%, over the previous best SPARTAN PS+TP1 and PS+TP2 partial scan ideas, respectively, on ISCAS '89 benchmark circuits. We also get 32.62% TV reduction and 25.39% TAT reduction over the mpscan algorithm.
NoteM.S.
NoteIncludes bibliographical references (p. 125-130)
Noteby Raghuveer Ausoori
Genretheses, ETD graduate
Persistent URLhttps://doi.org/doi:10.7282/T3H70FXN
Languageeng
CollectionGraduate School - New Brunswick Electronic Theses and Dissertations
Organization NameRutgers, The State University of New Jersey
RightsThe author owns the copyright to this work.
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