Sarode, Onkar. Architecture of a programmable system-on-chip platform for flexible radio processing. Retrieved from https://doi.org/doi:10.7282/T3CF9PTF
DescriptionThe emergence of multiple radio access technologies (RATs) and their continuous evolution, is driving the need for programmable radio processing. Programmable radio devices with run-time flexibility and resource virtualization features will not only enable faster time-to-market, longer lifetime of devices, and universal connectivity, but also act as building blocks for advanced wireless technologies of adaptive and cognitive radios. These requirements have forced a shift from the traditional ASIC approach. However, most existing flexible solutions are based on either fully software-defined or software-controlled approaches that lack the power efficiency, performance and determinism (for real-time constraints) needed for wireless processing. In this thesis, we propose a programmable multi-processor system-on-chip (SoC) platform architecture based on a novel Virtual Flow Pipelining (VFP) framework that aims at striking a balance between flexibility (as provided by SDR) and performance (as provided by ASICs). The key highlights of this concept are a simple task-level programming model for provisioning protocol flows, and the use of dedicated hardware-based OS-like support for controlling their run-time execution. We present the evolution of a clustering-based organization for the SoC with distributed-shared controllers. Clustering along with an inherent architectural support for message passing provides a balance between scalability and hardware overhead. Shared controllers with a pipelined microarchitecture and a separate interconnect for control messaging are designed for low hardware complexity and high performance. The proposed architecture is evaluated by creating a bit- and cycle-accurate model in synthesizable register-transfer-level (RTL). It has been built into a virtual platform for 802.11a transmitter, which has successfully executed single and multiple flows for rates of 6, 12 and 24 Mbps. This thesis also presents a characterization and analysis of the architecture to provide key implications such as control overhead for different task sizes, its impact on cluster size etc.