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Architecture of a programmable system-on-chip platform for flexible radio processing
Descriptive
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Text
TitleInfo
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Title
Architecture of a programmable system-on-chip platform for flexible radio processing
Identifier
ETD_2945
Identifier
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http://hdl.rutgers.edu/1782.1/rucore10001600001.ETD.000056765
Language
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eng
Genre
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theses
Subject
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Topic
Electrical and Computer Engineering
Subject
(ID = SBJ-2);
(authority = ETD-LCSH)
Topic
Cognitive radio networks
Subject
(ID = SBJ-3);
(authority = ETD-LCSH)
Topic
Computer architecture
Abstract
(type = abstract)
The emergence of multiple radio access technologies (RATs) and their continuous evolution, is driving the need for programmable radio processing. Programmable radio devices with run-time flexibility and resource virtualization features will not only enable faster time-to-market, longer lifetime of devices, and universal connectivity, but also act as building blocks for advanced wireless technologies of adaptive and cognitive radios. These requirements have forced a shift from the traditional ASIC approach. However, most existing flexible solutions are based on either fully software-defined or software-controlled approaches that lack the power efficiency, performance and determinism (for real-time constraints) needed for wireless processing. In this thesis, we propose a programmable multi-processor system-on-chip (SoC) platform architecture based on a novel Virtual Flow Pipelining (VFP) framework that aims at striking a balance between flexibility (as provided by SDR) and performance (as provided by ASICs). The key highlights of this concept are a simple task-level programming model for provisioning protocol flows, and the use of dedicated hardware-based OS-like support for controlling their run-time execution. We present the evolution of a clustering-based organization for the SoC with distributed-shared controllers. Clustering along with an inherent architectural support for message passing provides a balance between scalability and hardware overhead. Shared controllers with a pipelined microarchitecture and a separate interconnect for control messaging are designed for low hardware complexity and high performance. The proposed architecture is evaluated by creating a bit- and cycle-accurate model in synthesizable register-transfer-level (RTL). It has been built into a virtual platform for 802.11a transmitter, which has successfully executed single and multiple flows for rates of 6, 12 and 24 Mbps. This thesis also presents a characterization and analysis of the architecture to provide key implications such as control overhead for different task sizes, its impact on cluster size etc.
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electronic resource
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ix, 77 p. : ill.
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Note
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M.S.
Note
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Includes bibliographical references
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by Onkar Sarode
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Sarode
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Onkar
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1983-
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author
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Onkar Sarode
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Spasojevic
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chair
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Predrag Spasojevic
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Zhang
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Yanyong
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internal member
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Yanyong Zhang
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Chakraborty
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Tapan
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Advisory Committee
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Tapan Chakraborty
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Miljanic
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Zoran
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outside member
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Advisory Committee
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Zoran Miljanic
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Rutgers University
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degree grantor
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Graduate School - New Brunswick
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school
OriginInfo
DateCreated
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2010
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2010-10
Place
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xx
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TitleInfo
Title
Rutgers University Electronic Theses and Dissertations
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ETD
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Title
Graduate School - New Brunswick Electronic Theses and Dissertations
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rucore19991600001
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NjNbRU
Identifier
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doi:10.7282/T3CF9PTF
Genre
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ETD graduate
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Rights
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The author owns the copyright to this work.
Copyright
Status
Copyright protected
Availability
Status
Open
Reason
Permission or license
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Name
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Sarode
GivenName
Onkar
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DateTime
2010-09-29 16:34:41
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Onkar Sarode
Affiliation
Rutgers University. Graduate School - New Brunswick
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Author Agreement License
Detail
I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
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Embargo
DateTime
2010-10-31
Detail
Access to this PDF has been restricted at the author's request. It will be publicly available after October 31st, 2011.
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ETD
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application/x-tar
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