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ASIP data-plane processor for multi-standard wireless protocol processing
Descriptive
TypeOfResource
Text
TitleInfo
(ID = T-1)
Title
ASIP data-plane processor for multi-standard wireless protocol processing
Identifier
ETD_2772
Identifier
(type = hdl)
http://hdl.rutgers.edu/1782.1/rucore10001600001.ETD.000056859
Language
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eng
Genre
(authority = marcgt)
theses
Subject
(ID = SBJ-1);
(authority = RUETD)
Topic
Electrical and Computer Engineering
Subject
(ID = SBJ-2);
(authority = ETD-LCSH)
Topic
Wireless Application Protocol (Computer network protocol)
Subject
(ID = SBJ-3);
(authority = ETD-LCSH)
Topic
Microprocessors
Subject
(ID = SBJ-4);
(authority = ETD-LCSH)
Topic
Wireless communication systems
Subject
(ID = SBJ-5);
(authority = ETD-LCSH)
Topic
Software architecture
Abstract
(type = abstract)
Evolving Multi-Protocol Multi-Band Software Defined Radio (SDR) devices aim at supporting multiple protocols seamlessly and efficiently. The design of such radios necessitates flexibility in physical layer processing, flexibility in routing packets through processing engines and flexibility in radio frequency reception/transmission. This dissertation addresses an efficient implementation of flexible physical layer processing (PHY) for Interleaving, De-Interleaving and linear Minimum Mean Square Error (MMSE) detection in Multiple Input Multiple Output (MIMO) receivers through Application Specific Instruction Set Processors (ASIPs). The thesis defines and develops a WINLAB cognitive radio (WiNC2R) compatible data-plane ASIP architecture along with suitable hardware-software partitioning of the Processing Engine unit. Given the requirement of very significant design time and the lack of the flexibility after design, dedicated ASIC for PHY may not be a viable option although it has the best performance among all available options. The software application running on general purpose processor cannot satisfy the throughput requirements of the wireless standards. ASIPs provide a better trade-off between flexibility and performance, with the advantage of considerably lower design time than ASICs. We design an efficient multi-standard (802.11a, 802.16e/m) supporting Interleaver/De-Interleaver ASIP, satisfying the throughput requirements for all the modulation-schemes/data-rates in both of the standards. It can be programmed to scale for supporting future wireless standards (that use Block Interleaving/De-Interleaving). We also study viability of a flexible MIMO MMSE detector ASIP supporting variable MR (Number of receiving antennas) * MT (Number of transmitting antennas) operations. We have analyzed the implementation of an hardware-centric algorithm for MIMO detection on an ASIP and also improved its performance with the help of techniques such as fixed point implementation, Single Instruction Multiple Data (SIMD) and Very Long Instruction Word (VLIW). Analysis of the design performance results for MIMO ASIP indicates the limitations of hardware-implementation-specific algorithms on ASIP. We also provide the account of design decisions such as custom ports, memory interfaces and registers that are added to the data-plane processor ASIPs in order to substitute them for dedicated hardware engines in the WiNC2R platform.
PhysicalDescription
Form
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electronic resource
Extent
x, 85 p. : ill.
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application/pdf
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text/xml
Note
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M.S.
Note
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Includes bibliographical references
Note
(type = statement of responsibility)
by Mohit Gopal Wani
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Wani
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Mohit Gopal
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1983-
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author
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Mohit Wani
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chair
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Predrag Spasojevic
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Chakraborty
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Tapan
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internal member
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Advisory Committee
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Tapan Chakraborty
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Raychaudhuri
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Dipankar
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Dipankar Raychaudhuri
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Miljanic
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Zoran
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Advisory Committee
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Zoran Miljanic
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Rutgers University
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degree grantor
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Graduate School - New Brunswick
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school
OriginInfo
DateCreated
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2010
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2010-10
Place
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xx
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Title
Rutgers University Electronic Theses and Dissertations
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ETD
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Title
Graduate School - New Brunswick Electronic Theses and Dissertations
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rucore19991600001
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NjNbRU
Identifier
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doi:10.7282/T3CR5T38
Genre
(authority = ExL-Esploro)
ETD graduate
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Rights
RightsDeclaration
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(ID = rulibRdec0006)
The author owns the copyright to this work.
Copyright
Status
Copyright protected
Availability
Status
Open
Reason
Permission or license
RightsHolder
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(type = personal)
Name
FamilyName
Wani
GivenName
Mohit
Role
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DateTime
2010-07-01 14:19:21
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Name
Mohit Wani
Affiliation
Rutgers University. Graduate School - New Brunswick
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License
Name
Author Agreement License
Detail
I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
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Technical
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ETD
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application/pdf
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application/x-tar
FileSize
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2252800
Checksum
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3ccc008587e20f77e72ae1d9d29f50fdedccedce
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