Staff View
Architectural support for virtual memory in GPUs

Descriptive

TitleInfo
Title
Architectural support for virtual memory in GPUs
Name (type = personal)
NamePart (type = family)
Pichai
NamePart (type = given)
Bharath
NamePart (type = date)
1987-
DisplayForm
Bharath Pichai
Role
RoleTerm (authority = RULIB)
author
Name (type = personal)
NamePart (type = family)
Bhattacharjee
NamePart (type = given)
Abhishek
DisplayForm
Abhishek Bhattacharjee
Affiliation
Advisory Committee
Role
RoleTerm (authority = RULIB)
chair
Name (type = personal)
NamePart (type = family)
Bianchini
NamePart (type = given)
Ricardo
DisplayForm
Ricardo Bianchini
Affiliation
Advisory Committee
Role
RoleTerm (authority = RULIB)
internal member
Name (type = personal)
NamePart (type = family)
Nguyen
NamePart (type = given)
Thu
DisplayForm
Thu Nguyen
Affiliation
Advisory Committee
Role
RoleTerm (authority = RULIB)
internal member
Name (type = corporate)
NamePart
Rutgers University
Role
RoleTerm (authority = RULIB)
degree grantor
Name (type = corporate)
NamePart
Graduate School - New Brunswick
Role
RoleTerm (authority = RULIB)
school
TypeOfResource
Text
Genre (authority = marcgt)
theses
OriginInfo
DateCreated (qualifier = exact)
2013
DateOther (qualifier = exact); (type = degree)
2013-10
Place
PlaceTerm (type = code)
xx
Language
LanguageTerm (authority = ISO639-2b); (type = code)
eng
Abstract (type = abstract)
The proliferation of heterogeneous compute platforms, of which CPU/GPU is a prevalent example, necessitates a manageable programming model to ensure widespread adoption. A key component of this is a shared unified address space between the heterogeneous units to obtain the programmability benefits of virtual memory. Indeed, processor vendors have already begun embracing heterogeneous systems with unified address spaces (e.g., Intel's Haswell, AMD's Berlin processor, and ARM's Mali and Cortex cores). We are the first to explore GPU Translation Lookaside Buffers (TLBs) and page table walkers for address translation in the context of shared virtual memory for heterogeneous systems. To exploit the programmability benefits of shared virtual memory, it is natural to consider mirroring CPUs and placing TLBs prior (or parallel) to cache accesses, making caches physically addressed. We show the performance challenges of such an approach and propose modest hardware augmentations to recover much of this lost performance. We then consider the impact of this approach on the design of general purpose GPU performance improvement schemes. We look at: (1) warp scheduling to increase cache hit rates; and (2) dynamic warp formation to mitigate control flow divergence overheads. We show that introducing cache-parallel address translation does pose challenges, but that modest optimizations can buy back much of this lost performance. In the CPU world, the programmability benefits of address translation and physically addressed caches have outweighed their performance overheads. This paper is the first to explore similar address translation mechanisms on GPUs. We find that while cache-parallel address translation does introduce non-trivial performance overheads, modestly TLB-aware designs can move performance losses into a range deemed acceptable in the CPU world. We presume this stake-in-the-ground design leaves room for improvement but hope the larger result, that a little TLB-awareness goes a long way in GPUs, sets the stage for future work in this fruitful area.
Subject (authority = RUETD)
Topic
Computer Science
RelatedItem (type = host)
TitleInfo
Title
Rutgers University Electronic Theses and Dissertations
Identifier (type = RULIB)
ETD
Identifier
ETD_5031
PhysicalDescription
Form (authority = gmd)
electronic resource
InternetMediaType
application/pdf
InternetMediaType
text/xml
Extent
ix, 43 p. : ill.
Note (type = degree)
M.S.
Note (type = bibliography)
Includes bibliographical references
Note (type = statement of responsibility)
by Bharath Subramanian Pichai
Subject (authority = ETD-LCSH)
Topic
Computer architecture
Subject (authority = ETD-LCSH)
Topic
Computer storage devices
Subject (authority = ETD-LCSH)
Topic
Graphics processing units
RelatedItem (type = host)
TitleInfo
Title
Graduate School - New Brunswick Electronic Theses and Dissertations
Identifier (type = local)
rucore19991600001
Location
PhysicalLocation (authority = marcorg); (displayLabel = Rutgers, The State University of New Jersey)
NjNbRU
Identifier (type = doi)
doi:10.7282/T33F4MPF
Genre (authority = ExL-Esploro)
ETD graduate
Back to the top

Rights

RightsDeclaration (ID = rulibRdec0006)
The author owns the copyright to this work.
RightsHolder (type = personal)
Name
FamilyName
Pichai
GivenName
Bharath
Role
Copyright Holder
RightsEvent
Type
Permission or license
DateTime (encoding = w3cdtf); (qualifier = exact); (point = start)
2013-09-23 16:48:44
AssociatedEntity
Name
Bharath Pichai
Role
Copyright holder
Affiliation
Rutgers University. Graduate School - New Brunswick
AssociatedObject
Type
License
Name
Author Agreement License
Detail
I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
Copyright
Status
Copyright protected
Availability
Status
Open
Reason
Permission or license
Back to the top

Technical

RULTechMD (ID = TECHNICAL1)
ContentModel
ETD
OperatingSystem (VERSION = 5.1)
windows xp
Back to the top
Version 8.5.5
Rutgers University Libraries - Copyright ©2024