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A GPU binary analysis framework for memory performance and safety
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Hayes, Ari B.. A GPU binary analysis framework for memory performance and safety. Retrieved from https://doi.org/doi:10.7282/t3-8xxf-ss68

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TitleA GPU binary analysis framework for memory performance and safety
NameHayes, Ari B. (author); Zhang, Zheng (chair); Zhang, Zheng (member); Kremer, Ulrich (member); Parashar, Manish (member); Ding, Chen (member); Rutgers University; School of Graduate Studies
Date Created2022
Other Date2022-05 (degree)
SubjectComputer science, Graphics processing units
Extent136 pages : illustrations
DescriptionGeneral-Purpose Graphics Processing Units (GPUs) have attained popularity for their massive concurrency. But with their relative infancy, as well as a prevalence of closed-source and proprietary technology, GPU software has not undergone the degree of optimization that CPU software has. In this work, we focus on NVIDIA's GPUs and the CUDA framework, but our techniques may be generalized to other GPU platforms. We develop a compiler which targets the low-level SASS assembly, rather than the high-level source code or the intermediate-level PTX assembly. This allows for a degree of tuning and modification not possible at higher levels. We reconstruct program information such as the control-flow graph and call graph, thereby permitting data flow analysis. Thanks to extensive reverse-engineering, our compiler retains compatibility with numerous versions of the CUDA framework and several generations of NVIDIA GPUs. We are able to improve memory performance with optimizations not available in the proprietary compiler. We perform memory-allocation across the multiple types of available on-chip memory, making full use of available resources including registers, scratchpad memory, and the L1 data cache. This further allows us to tune occupancy - the number of threads allowed to be simultaneously active. We perform static and dynamic occupancy tuning, in order to find an effective balance between concurrency and resource contention. Our compiler can also be applied toward improvement of memory safety. We use it to implement dynamic taint tracking, a technique previously used on CPUs to identify sensitive data as it spreads through memory. By analyzing and modifying the low-level assembly, we minimize tracking overhead, track memory resources not visible to the programmer, and erase sensitive data before it has opportunity to leak. We evaluate our compiler across a number of benchmarks on NVIDIA devices of the Fermi, Kepler, Maxwell, and Pascal architectures. We demonstrate that our resource allocation and occupancy tuning provides significant improvement in both speed and energy usage. We additionally show that our GPU-specific optimizations for taint tracking can enormously reduce overhead.
NotePh.D.
NoteIncludes bibliographical references
Genretheses
Persistent URLhttps://doi.org/doi:10.7282/t3-8xxf-ss68
LanguageEnglish
CollectionSchool of Graduate Studies Electronic Theses and Dissertations
Organization NameRutgers, The State University of New Jersey
RightsThe author owns the copyright to this work.
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