Text

theses

Frequency synthesizers are widely being used for generating local oscillators for majority of RF, wireless, communication, and navigation systems for the last few decades. Phase-locked-loops (PLL) on the other hand are one of the fundamental portions of any digital/mixed-signal devices in addition to the previously mentioned systems. In this thesis work, a PLL based fractional-N frequency synthesizer for 2.4 GHz and 5 GHz wireless local area network (WLAN) in 0.18 μm CMOS-RF process has been proposed. With the adoption of a MASH 1-1-1 delta-sigma modulator facilitating fractional division ratios through a programmable divider, the frequency synthesizer differs from its integer-N counterpart in its higher reference frequency, wider loop bandwidth, faster settling time, and better phase noise and suppression of spurious tones. The synthesizer consists of several blocks, including a wide range LC-tuned voltage controlled oscillator (VCO), divide by 16 – 252 programmable divider, dead-zone free phase-frequency detector (PFD), low mismatch high swing cascode charge pump (CP), 3rd order loop filter (LF), and a 3rd order MASH delta-sigma modulator (DSM)—all of which have been designed and constructed in both transistor and layout levels. SPICE (BSIM3) level simulations have been performed for all the individual blocks as well as the complete frequency synthesizer for extracting transient, DC, periodic-steady-state, and phase-noise analyses results. Overall, with 1.2 V supply voltage, the 0.628 mm X 0.594 mm fractional-N frequency synthesizer achieves “locked” state in approximately 2 μs and produces approximately -111 dBc/Hz phase noise at 1 MHz offset (excluding the MASH modulator) while consuming about 20.76 mW of power.

ETD_6766

M.S.

Includes bibliographical references

by Subrata Debnath

doi:10.7282/T3N29ZXS

ETD graduate

The author owns the copyright to this work.