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High-throughput FPGA QC-LDPC decoder architecture for 5G wireless
Descriptive
TitleInfo
Title
High-throughput FPGA QC-LDPC decoder architecture for 5G wireless
Name
(type = personal)
NamePart
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Mhaske
NamePart
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Swapnil
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Swapnil Mhaske
Role
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(authority = RULIB)
author
Name
(type = personal)
NamePart
(type = family)
Spasojevic
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(type = given)
Predrag
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Predrag Spasojevic
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Advisory Committee
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chair
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(type = family)
Yates
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(type = given)
Roy
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Roy Yates
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Advisory Committee
Role
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(authority = RULIB)
internal member
Name
(type = personal)
NamePart
(type = family)
Gajic
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(type = given)
Zoran
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Zoran Gajic
Affiliation
Advisory Committee
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internal member
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Rutgers University
Role
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(authority = RULIB)
degree grantor
Name
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NamePart
Graduate School - New Brunswick
Role
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school
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Text
Genre
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theses
OriginInfo
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2015
DateOther
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(type = degree)
2015-10
CopyrightDate
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(qualifier = exact)
2015
Place
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xx
Language
LanguageTerm
(authority = ISO639-2b);
(type = code)
eng
Abstract
(type = abstract)
Wireless data traffic is expected to increase by a 1000 fold by the year 2020 with more than 50 billion devices connected to these wireless networks with peak data rates upto 10 Gb/s. The next generation of wireless cellular technology (being collectively termed as 5G) is slated to operate in the mm-wave (30-300GHz) spectrum which comes with challenges such as, reliance on line of sight (LOS) communication, short range of communication, increased shadowing and, rapid fading in time. This will necessitate additional signal processing techniques such as large antenna arrays and beamsteering which will further reduce the processing budget available to the channel coding system. In an effort ort to design and develop a channel coding solution suitable to such systems, in this thesis we propose strategies to achieve a high-throughput FPGA-based decoder architecture for a QC-LDPC code based on circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multifold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining of blocks and hence layers. By partitioning the PCM into not only layers but superlayers, we derive an upper bound on the pipelining depth with respect to the size of the superlayer for the compact representation. To validate the architecture, a decoder for the IEEE 802.11n (2012) QC-LDPC is implemented on the Xilinx Kintex-7 FPGA with the help of the FPGA IP compiler available in the NI LabVIEW Communication System Design Suite (CSDS). It off ers an automated and systematic compilation flow. An optimized hardware implementation from the decoder algorithm was generated in approximately 3 minutes, achieving an overall throughput of 608Mb/s (at 260MHz). With little or no modi fications, the proposed decoder architecture caters to a wide range of circulant-1 identity matrix construction based QC-LDPC codes widely accepted in several communication and data storage standards.
Subject
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Topic
Electrical and Computer Engineering
RelatedItem
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TitleInfo
Title
Rutgers University Electronic Theses and Dissertations
Identifier
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ETD
Identifier
ETD_6719
PhysicalDescription
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electronic resource
InternetMediaType
application/pdf
InternetMediaType
text/xml
Extent
1 online resource (x, 42 p. : ill.)
Note
(type = degree)
M.S.
Note
(type = bibliography)
Includes bibliographical references
Subject
(authority = ETD-LCSH)
Topic
Modulation (Electronics)
Subject
(authority = ETD-LCSH)
Topic
Wireless communication systems
Note
(type = statement of responsibility)
by Swapnil Mhaske
RelatedItem
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TitleInfo
Title
Graduate School - New Brunswick Electronic Theses and Dissertations
Identifier
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rucore19991600001
Location
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(displayLabel = Rutgers, The State University of New Jersey)
NjNbRU
Identifier
(type = doi)
doi:10.7282/T3JH3P5W
Genre
(authority = ExL-Esploro)
ETD graduate
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Rights
RightsDeclaration
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The author owns the copyright to this work.
RightsHolder
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Name
FamilyName
Mhaske
GivenName
Swapnil
Role
Copyright Holder
RightsEvent
Type
Permission or license
DateTime
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(point = start)
2015-09-09 17:16:34
AssociatedEntity
Name
Swapnil Mhaske
Role
Copyright holder
Affiliation
Rutgers University. Graduate School - New Brunswick
AssociatedObject
Type
License
Name
Author Agreement License
Detail
I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
Copyright
Status
Copyright protected
Availability
Status
Open
Reason
Permission or license
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Technical
RULTechMD
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ETD
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windows xp
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