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Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits
Descriptive
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Title
Jitter reduction circuits to reduce the bit-error rate of high-speed serializer-deserializer (SERDES) circuits
Name
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Venkatanarayanan
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Hari Vijay
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Hari Vijay Venkatanarayanan
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author
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Bushnell
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Michael
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Advisory Committee
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Michael L. Bushnell
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dissertation committee chair
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Sheng
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Kuang
Affiliation
Advisory Committee
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Kuang Sheng
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internal member
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Rabiner
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Lawrence
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Advisory Committee
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Lawrence Rabiner
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dissertation committee member
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Chakraborty
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Tapan
Affiliation
Advisory Committee
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Tapan J Chakraborty
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outside member
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Rutgers University
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degree grantor
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Graduate School - New Brunswick
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school
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theses
OriginInfo
DateCreated
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2008
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2008-01
Language
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English
PhysicalDescription
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electronic
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application/pdf
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text/xml
Extent
xv, 142 pages
Abstract
A new jitter reduction technique is proposed for reducing the timing jitter in a serializer-deserializer (SERDES) circuit. The technique involves transmit and receive side jitter reducer circuits made of only 14 and 20 transistors, respectively. They reduce the jitter in the clock generated by the phase-locked-loop (PLL) at the transmit side, and the jitter between the recovered clock and the serial data at the receive side. The jitter reducers are designed using 70nm Berkeley Predictive process models and tested with various types of input jitter. In the case of the transmit side jitter reducer, the jitter is reduced, on average, by 62.24%. The performance of the jitter reducer is compared with the adaptive PLL technique proposed by Xia et al. [39] in terms of the peak-to-peak jitter reduction. The peak-to-peak jitter is reduced, on average, by 45.51% using the transmit side jitter reducer. For the receive side jitter reducer, the jitter is reduced, on average, by 35.88%. The SERDES circuit is then tested for its jitter performance under three conditions: (1) no jitter reducers are present, (2) the receive side jitter reducer is present and (3) both transmit and receive side jitter reducers are present. In each of these cases, the bit-error rate (BER) is computed probabilistically and is shown to improve from 8.3 x 10-2 to 6.44 x 10-20, for input RMS periodic jitter (PJ) of 71.77 ps. Finally, a SERDES test scheme is used to test the jitter reducers for their stuck-at faults and then to perform the receiver jitter tolerance and BER tests.
Note
(type = degree)
Ph.D.
Note
(type = bibliography)
Includes bibliographical references (p. 137-140).
Subject
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Topic
Electrical and Computer Engineering
Subject
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Topic
Integrated circuits
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Title
Graduate School - New Brunswick Electronic Theses and Dissertations
Identifier
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rucore19991600001
Identifier
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http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.17259
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ETD_594
Location
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NjNbRU
Identifier
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doi:10.7282/T3833SDN
Genre
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ETD doctoral
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Rights
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The author owns the copyright to this work.
Copyright
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Copyright protected
Availability
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Open
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Name
HARI VIJAY VENKATANARAYANAN
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Copyright holder
Affiliation
Rutgers University. Graduate School - New Brunswick
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Non-exclusive ETD license
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Author Agreement License
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I hereby grant to the Rutgers University Libraries and to my school the non-exclusive right to archive, reproduce and distribute my thesis or dissertation, in whole or in part, and/or my abstract, in whole or in part, in and from an electronic format, subject to the release date subsequently stipulated in this submittal form and approved by my school. I represent and stipulate that the thesis or dissertation and its abstract are my original work, that they do not infringe or violate any rights of others, and that I make these grants as the sole owner of the rights to my thesis or dissertation and its abstract. I represent that I have obtained written permissions, when necessary, from the owner(s) of each third party copyrighted matter to be included in my thesis or dissertation and will supply copies of such upon request by my school. I acknowledge that RU ETD and my school will not distribute my thesis or dissertation or its abstract if, in their reasonable judgment, they believe all such rights have not been secured. I acknowledge that I retain ownership rights to the copyright of my work. I also retain the right to use all or part of this thesis or dissertation in future works, such as articles or books.
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