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Improving and complementing virtual memory using hardware techniques
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Albuquerque Cox, Guilherme. Improving and complementing virtual memory using hardware techniques. Retrieved from https://doi.org/doi:10.7282/t3-m0cq-tt95

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TitleImproving and complementing virtual memory using hardware techniques
NameAlbuquerque Cox, Guilherme (author); Bhattacharjee, Abhishek (chair); Ganapathy, Vinod (internal member); Kremer, Ulrich (internal member); Lustig, Daniel (outside member); Rutgers University; School of Graduate Studies
Date Created2018
Other Date2018-10 (degree)
SubjectComputer Science, Virtual storage (Computer science), Cloud computing
Extent1 online resource (160 pages) : illustrations
DescriptionVirtual memory is a classic computer science abstraction and is ubiquitous in all scales of computing today. However, despite years of research, virtual memory faces critical performance and security challenges. This thesis aims to address these challenges. The first challenge we address is the growing performance overheads faced by virtual memory as workloads continue demanding ever-increasing amounts of memory. The key culprit of these overheads is address translation, the mechanism by which virtual memory translates a program's virtual addresses to physical addresses. Performing fast address translation requires the design of fast and efficient hardware translation lookaside buffer (TLB) caches. Unfortunately, TLBs struggle to perform efficiently for ``big data" workloads. This thesis proposes a range of hardware mechanisms to improve TLB performance. The second challenge we address pertains to the security mechanisms offered by the virtual memory abstraction through memory protection and process isolation. Despite their utility, protection/isolation are insufficient to avoid important classes of remote attacks. Attackers can corrupt the operating system and thereby gain control of the entire machine. Therefore, there is a need for security mechanisms complementary to those provided by virtual memory. We propose low-overhead mechanisms achieve this. Our approach is to build hardware that can snapshot physical memory in an efficient manner, so that we can enable faster/better memory forensics to enhance system security.

Both sets of studies highlight some important themes in this thesis. One unifying theme of our work is to build hardware mechanisms that are transparent to application developers and systems programmers. Another unifying theme is ease of implementation -- we deliberately use hardware mechanisms that require modest hardware modifications. In situations when the modifications are more substantial, we formally verify the correctness of our approach. Finally, we quantify the benefits of our approaches using not only software performance models (like most architecture studies), but also go beyond by quantifying real-system performance when possible.
NotePh.D.
NoteIncludes bibliographical references
Noteby Guilherme Mota Cavalcanti de Albuquerque Cox
Genretheses, ETD doctoral
Persistent URLhttps://doi.org/doi:10.7282/t3-m0cq-tt95
Languageeng
CollectionSchool of Graduate Studies Electronic Theses and Dissertations
Organization NameRutgers, The State University of New Jersey
RightsThe author owns the copyright to this work.
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